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| fujitsu microelectronics data sheet copyright?2004-2009 fujitsu microelec tronics limited all rights reserved 2009.8 for the information for microcontrolle r supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90895 series mb90f897/f897s/f897y* 1 /f897ys* 1 / mb90v495g description mb90895 series devices are 16-bit general-purpose microc ontrollers designed for app lications which need high- speed real-time processing. the devices of this series are high-performance 16-bit cpu microcontrollers em- ploying of the dual operation flash memory a nd can controller on lqfp-48 small package. the system, inheriting the architecture of f 2 mc* 2 family, employs additional instruction ready for high-level lan- guages, expanded addressing mode, enhanc ed multiply-divide instructions, and enriched bit-processing instruc- tions. furthermore, employment of 32-bit accumulato r achieves processing of long-word data (32 bits). the peripheral resources of mb90895 series include the following: 8/10-bit a/d converter, uart0/uart1 (sci), 8/16-bit pp g timer, 16-bit input-output timer (16-bit free-run timer, input capture 0, 1, 2, 3 (icu)), and can controller. *1 : these devices are under development. this datasheet provides preliminary information for the devices under development. *2 : ?f 2 mc? is the abbreviation of fujitsu flexible microcontroller. features ? models that support +125 c (mb90f897/s) ? models that support +150 c (mb90f897y/ys) ? clock ? built-in pll clock frequency multiplication circuit ? selection of machine clocks (pll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-mhz oscillation clock, 4 mhz to 16 mhz). ? operation by sub-clock (8.192 khz) is allowed. (mb90f897/y) ? minimum execution time of instructi on: 62.5 ns (when operating with 4-mh z oscillation clock, and 4-time multi- plied pll clock). ? 16 mbyte cpu memory space ? 24-bit internal addressing (continued) ds07-13731-5e
mb90895 series 2 ds07-13731-5e (continued) ? instruction system best suited to controller ? wide choice of data types (bit, byte, word, and long word) ? wide choice of addressing modes (23 types) ? enhanced multiply-divide instru ctions and reti instructions ? enhanced high-precision computing with 32-bit accumulator ? instruction system compatible with high- level language (c language) and multitask ? employing system stack pointer ? enhanced various pointer indirect instructions ? barrel shift instructions ? increased processing speed ? 4-byte instruction queue ? powerful interrupt function with 8 levels and 34 factors ? automatic data transfer fu nction independent of cpu ? extended intelligent i/o service function (ei 2 os): maximum of 16 channels ? low power consumption (standby) mode ? sleep mode (a mode that halts cpu operating clock) ? time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and watch timer only) ? watch mode (a mode that operate s sub clock and watch timer only) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu intermittent operation mode ? process ?cmos technology ? i/o port ? general-purpose input/output port (cmos output) : mb90f897/y : 34 ports (including 4 high-current output ports) mb90f897s/ys : 36 ports (including 4 high-current output ports) ? timer ? time-base timer, watch timer, watchdog timer: 1 channel ? 8/16-bit ppg timer: 8-bit x 4 channels, or 16-bit x 2 channels ? 16-bit reload timer: 2 channels ? 16-bit input/output timer - 16-bit free run timer: 1 channel - 16-bit input capture: (icu): 4 channels interrupt request is issued upon latching a count value of 16-bi t free run timer by detection of an edge on pin input. ? can controller: 1 channel ? complied with ver 2.0a and ver 2.0b can specifications ? 8 built-in message buffers ? transmission rate of 10 kbps to 1 mbps (by 16 mhz machine clock) ?can wake-up ? uart0 (sci), uart1(sci): 2 channels ? equipped with full-duplex double buffer ? clock-asynchronous or clock-synchronous serial transmission is available. ? dtp/external interrupt: 4 channels, can wake-up: 1channel ? module for activation of extended intelligent i/o service (ei 2 os), and generation of external interrupt. ? delay interrupt generator module ? generates interrupt request for task switching. ? 8/10-bit a/d converter: 8 channels ? resolution is selectable between 8-bit and 10-bit. ? activation by external trigger input is allowed. ? conversion time: 6.125 s (at 16-mhz machine clock, including sampling time) ? program patch function ? address matching detection for 2 address pointers. mb90895 series ds07-13731-5e 3 product lineup (continued) part number parameter mb90f897 mb90f897s mb90f897y (under development) mb90f897ys (under development) mb90v495g classification flash rom evaluation product rom capacity 64 kbytes ? ram capacity 2 kbytes 6 kbytes process cmos package lqfp-48 (pin pitch 0.50 mm) pga256 operating power supply voltage 3. 5 v to 5.5 v 4.5 v to 5.5 v special power supply for emulator* 1 ? none cpu functions number of basic instructions : 351 instructions instruction length : 1 byte to 7 bytes data bit length : 1 bit, 8 bits, 16 bits minimum instruction execution time : 62.5 ns (at 16-mhz machine clock) interrupt processing time : 1.5 s at minimum (at 16-mhz machine clock) low power consumption (standby) mode sleep mode/watch mode/time-base timer mode/ stop mode/cpu intermittent i/o port general-purpose input/output ports (cmos output) : 34 ports (36 ports* 2 ) including 4 high-current output ports (p14 to p17) time-base timer 18-bit free-run counter interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with oscillation cloc k frequency at 4 mhz) watchdog timer reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with oscillation cloc k frequency at 4 mhz) 16-bit input/output timer 16-bit free-run timer number of channels: 1 interrupt upon occurrence of overflow input capture number of channels: 4 retaining free-run timer value set by pin input (rising edge, falling edge, and both edges) 16-bit reload timer number of channels: 2 16-bit reload timer operation count clock cycle: 0.25 s, 0.5 s, 2.0 s (at 16-mhz machine clock frequency) external event count is allowed. watch timer 15-bit free-run counter interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192 khz sub clock) 8/16-bit ppg timer number of channels: 2 (four 8-bi t channels are available also.) ppg operation is allowed with four 8-bit channels or one 16-bit channel. outputting pulse wave of arbitrary cycle or arbitrary duty is allowed. count clock: 62.5 ns to 1 s (with 16 mhz machine clock) delay interrupt generator module interrupt generator m odule for task switching. used for real-time os. mb90895 series 4 ds07-13731-5e (continued) *1 : settings of dip switch s2 for using emulation pod mb2145-507. for details, see mb2145-507 hardware manual (2.7 power pin solely for emulator). *2 : mb90f897s/ys packages and product models : yes, : no note : refer to ? package dimension? for details of the package. part number parameter mb90f897 mb90f897s mb90f897y (under development) mb90f897ys (under development) mb90v495g dtp/external interrupt number of inputs: 4 activated by rising edge, falling edge, ?h? level or ?l? level input. external interrupt or extended intelligent i/o service (ei 2 os) is available. 8/10-bit a/d converter number of channels: 8 resolution: selectable 10-bit or 8-bit. conversion time: 6.125 s (at 16-mhz machine clock, including sampling time) sequential conversion of two or more su ccessive channels is allowed. (setting a maximum of 8 channels is allowed.) single conversion mode : selected channel is converted only once. sequential conversion mode: selected channel is converted repetitively. halt conversion mode : conversion of selected channel is stopped and activated alternately. uart0 (sci) number of channels: 1 clock-synchronous transfer: 62.5 kbps to 2 mbps clock-asynchronous transfer: 1,202 bps to 62,500 bps communication is allowed by bi-directional serial communication function and master/slave type connection. uart1 (sci) number of channels: 1 clock-synchronous transfer: 62.5 kbps to 2 mbps clock-asynchronous transf er: 9,615 bps to 500 kbps communication is allowed by bi-directional serial communication function and master/slave type connection. can complied with ver 2.0a and ver 2.0b can specifications. 8 built-in message buffers. transmission rate of 10 kbps to 1 mbps (by 16 mhz machine clock) can wake-up package mb90f897/s/y/ys fpt-48p-m26 mb90895 series ds07-13731-5e 5 product comparison memory space when testing with test product for evaluation, check the differences between the product and a product to be used actually. pay attention to the following points: ? the mb90v495g has no built-in rom. however, a sp ecial-purpose development tool allows the operations as those of one with built-in rom. rom capa city depends on settings on a development tool. ? on mb90v495g, an image from ff4000 h to ffffff h is viewed on 00 bank and an image of fe0000 h to ff3fff h is viewed only on fe bank and ff bank. (modified on se ttings of a development tool.) ? on mb90f897/s/y/ys, an image from ff4000 h to ffffff h is viewed on 00 bank and an image of ff0000 h to ff3fff h is viewed only on ff bank. mb90895 series 6 ds07-13731-5e pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 lqfp-48 av cc avr p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p37/adtg p20/tin0 36 35 34 33 32 31 30 29 28 27 26 25 p17/ppg3 p16/ppg2 p15/ppg1 p14/ppg0 p13/in3 p12/in2 p11/in1 p10/in0 x1 x0 c v ss 48 47 46 45 44 43 42 41 40 39 38 37 av ss x1a/p36* x0a/p35* p33 p32/sin0 p31sck0 p30/s ot0 p44/rx p43/tx p42/s ot1 p41/sck1 p40/sin1 13 14 15 16 17 18 19 20 21 22 23 24 p21/tot0 p22/tin1 p23 /tot1 p24/int4 p25/int5 p26/int6 p27/int7 md2 md1 md0 rst v cc (fpt-48p-m26) (top view) *: mb90f897/y : x1a, x0a mb90f897s/ys : p36, p35 mb90895 series ds07-13731-5e 7 pin description (continued) pin no. pin name circuit type function 1avcc ? vcc power input pin for a/d converter. 2 avr ? power (vref+) input pin for a/d converter. use as input for vcc or lower. 3 to 10 p50 to p57 e general-purpose input/output ports. an0 to an7 functions as analog input pin for a/d converter. valid when analog input setting is ?enabled.? 11 p37 d general-purpose input/output ports. adtg function as an external trigger input pin for a/d converter. use the pin by setting as input port. 12 p20 d general-purpose input/output ports. tin0 function as an event input pin for reload timer 0. use the pin by setting as input port. 13 p21 d general-purpose input/output ports. tot0 function as an event output pin for reload timer 0. valid only when output setting is ?enabled.? 14 p22 d general-purpose input/output ports. tin1 function as an event input pin for reload timer 1. use the pin by setting as input port. 15 p23 d general-purpose input/output ports. tot1 function as an event output pin for reload timer 1. valid only when output setting is ?enabled.? 16 to 19 p24 to p27 d general-purpose input/output ports. int4 to int7 functions as external interrupt input pin. use the pin by setting as input port. 20 md2 f input pin for specifying operatio n mode. connect directly to vss. 21 md1 c input pin for specifying operatio n mode. connect directly to vcc. 22 md0 c input pin for specifying operatio n mode. connect directly to vcc. 23 rst b external reset input pin. 24 vcc ? power supply (5 v) input pin. 25 vss ? power supply (0 v) input pin. 26 c ? capacitor pin for stabilizing power su pply. connect a ceramic capacitor of approximately 0.1 f. 27 x0 a pin for high-rate oscillation. 28 x1 a pin for high-rate oscillation. 29 to 32 p10 to p13 d general-purpose input/output ports. in0 to in3 functions as trigger input pins of i nput capture channels 0 to 3. use the pins by setting as input ports. mb90895 series 8 ds07-13731-5e (continued) * : mb90f897/y : x1a, x0a mb90f897s/ys : p36, p35 pin no. pin name circuit type function 33 to 36 p14 to p17 g general-purpose input/output ports. high-current output ports. ppg0 to ppg3 functions as output pin of ppg time rs 01 and 23. valid when output setting is ?enabled.? 37 p40 d general-purpose input/output port. sin1 serial data input pin for uart1. us e the pin by setting as input port. 38 p41 d general-purpose input/output port. sck1 serial clock input/output pin for uart 1. valid only when serial clock input/ output setting on uart1 is ?enabled.? 39 p42 d general-purpose input/output port. sot1 serial data output pin for uart1. va lid only when serial data output setting on uart1 is ?enabled.? 40 p43 d general-purpose input/output port. tx transmission output pin for can. valid only when output setting is ?enabled.? 41 p44 d general-purpose input/output port. rx receive input pin for can. use th e pin by setting as input port. 42 p30 d general-purpose input/output port. sot0 serial data output pin for uart0. va lid only when serial data output setting on uart0 is ?enabled.? 43 p31 d general-purpose input/output port. sck0 serial clock input/output pin for uart 0. valid only when serial clock input/ output setting on uart0 is ?enabled.? 44 p32 h general-purpose input/output port. sin0 serial data input/output pin for uart0. use the pin by setting as input port. 45 p33 d general-purpose input/output port. 46 x0a* a pin for low-rate oscillation. p35* general-purpose input/output port. 47 x1a* a pin for low-rate oscillation. p36* general-purpose input/output port. 48 avss ? vss power supply input pin for a/d converter. mb90895 series ds07-13731-5e 9 i/o circuit type (continued) type circuit remarks a ? high-rate oscillation feedback resistor, approx. 1 m ? low-rate oscillation feedback resistor, approx. 10 m b ? hysteresis input with pull-up resistor. ? pull-up resistor, approx. 50 k c hysteresis input d ? cmos hysteresis input ? cmos level output ? standby control provided ? automotive input e ? cmos hysteresis input ? cmos level output ? shared for analog input pin ? standby control provided ? automotive input x1 x1a x0 x0a clock input standby control signal r vcc r hysteresis input r hysteresis input r p-ch n-ch vcc vss r digital output digital output hysteresis input standby control automotive input r p-ch n-ch vcc vss r digital output digital output hysteresis input standby control analog input automotive input mb90895 series 10 ds07-13731-5e (continued) type circuit remarks f ? hysteresis input with pull-down resistor ? pull-down resistor, approx. 50 k ? flash product is not provided with pull-down resistor. g ? cmos hysteresis input ? cmos level output (high-current output) ? standby control provided ? automotive input h ? cmos hysteresis input ? cmos level output ? standby control provided ? cmos input ? automotive input vss r r hysteresis input r p-ch n-ch vcc vss r high-current output high-current output hysteresis input standby control automotive input r p-ch vcc vss r r hysteresis input standby control digital output digital output automotive input cmos input mb90895 series ds07-13731-5e 11 handling devices ? do not exceed maximum rating (preventing ?latch up?) ? latch-up may occur in a cmos ic if a voltage higher than v cc or less than v ss is applied to an input or output pin or if a voltage exceeding the rated value is applied between v cc pin and v ss pins. ? latch-up causes drastic increase of power current, whic h may lead to destruction of elements by heat. extreme caution must be taken not to exceed maximum rating. ? when turning on and off analog power supply, take ex tra care not to apply an analog power voltages (avcc and avr) and analog input voltage that ar e higher than digital power voltage (vcc). ? handling unused pins ? leaving unused input pins open ma y cause permanent destruction by malfunction or latch-up. apply pull-up or pull-down process to the unused pins using resistors of 2 k or higher. leave unused i/o pins open under output status, or process as input pi ns if they are under input status. ? using external clock ? when using an external clock, drive only x0 pin and leave x1 pin open. an example of using an external clock is shown below. ? notes when using no sub clock on mb90f897/y ? if an oscillator is not connected to x0a and x1a pins, apply pull-down resistor to the x0a pin and leave the x1a pin open. ? about power supply pins ? if two or more vcc and vss exist, the pins that should be at the same potential are connected to each other inside the device. for reducing unwanted emissions and preventing malfunction of strobe signals caused by increase of ground level, however, be sure to connect the vcc and vss pi ns to the power supply and the ground externally. ? pay attention to connect a power supply to vcc and vs s pins of mb90895 series device in a lowest-possible impedance. ? near pins of mb90895 series device, connecting a bypass capacitor is recommended at 0.1 f across vcc and vss pins. ? crystal oscillator circuit ? noises around x0 and x1 pins cause malfunctions on a mb90895 series device. design a print circuit so that x0 and x1 pins, an crystal oscillator (or a ceramic osc illator), and bypass capacitor to the ground become as close as possible to each other. furthermore, avoid wire s to x0 and x1 pins crossing each other as much as possible. ? print circuit designing that surrounds x0 and x1 pins with grounding wires, which ensures stable operation, is strongly recommended. x1 x0 open mb90895 series ? using external clock mb90895 series 12 ds07-13731-5e ? caution on operations during pll clock mode ? if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. ? sequence of turning on power of a/ d converter and applying analog input ? be sure to turn on digital power (vcc) before apply ing signals to the a/d converter and applying analog input signals (an0 to an7 pins). ? be sure to turn off the power of a/d converter and analog input before turning off the digital power supply. ? be sure not to apply avr exceeding avcc when turning on and off. (no pr oblems occur if analog and digital power is turned on and off simultaneously.) ? handling pins when a/d converter is not used ? if the a/d converter is not used, connect the pins under the following conditions: ?avcc=avr=vcc,? and ?avss=vss?. ? note on turning on power ? for preventing malfunctions on built-in st ep-down circuit, maintain a minimum of 50 s of voltage rising time (between 0.2 v and 2.7 v) when turning on the power. ? stabilization of supply voltage ? a sudden change in the supply voltage may cause the device to malfunction even within the specified v cc supply voltage operating range. therefore, the v cc supply voltage should be stabilized. for reference, the supply volt age should be controlled so that v cc ripple variations (peak-to-peak values) at commercial frequencies (50 / 60hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. ? support for +125 c / +150 c ? users considering application exceeding t a = +105 c are advised to contact their representatives beforehand for reliability limitations. mb90895 series ds07-13731-5e 13 block diagram in0 to in3 ram flash int4 to int7 rx tx ppg0 to ppg3 tin0,tin1 tot0,tot1 x0a,x1a rst x0,x1 sck1 s ot1 sin1 avcc an0 to an7 av ss avr adtg uart1 can sck0 s ot0 sin0 uart0 clock control circuit watch timer time-base timer prescaler cpu f 2 mc-16lx core 16-bit free-run timer input capture (4ch) 16-bit ppg timer (2ch) 16-bit reload timer (2ch) dtp/external interrupt 8/10-bit a/d converter (8ch) internal data bus prescaler mb90895 series 14 ds07-13731-5e memory map 1. memory allocation of mb90895 mb90895 series model outputs 24-bit wide internal addre ss bus and up to 24-bit of external address bus. a maximum of 16 mbyte memory space of external access memory is accessible. 2. memory map note : when internal rom is operating, f 2 mc-16lx allows viewing rom data im age on ff bank at upper-level of 00 bank. this function is called ?mirroring rom,? wh ich allows effective use of c compiler small model. f 2 mc-16lx assigns the same low order 16-bit address to ff bank and 00 bank, which allows referencing table in rom without specifying ?far? using pointer. for example, when accessing to ?00c000 h ?, rom data at ?ffc000 h ? is accessed actually. however, because rom area of ff bank exceeds 48 kbytes, viewing all areas is not possible on 00 bank image. because rom data of ?ff4000 h ? to ?ffffff h ? is viewed on ?004000 h ? to ?00ffff h ? image, store a rom data table in area ?ff4000 h ? to ?ffffff h .? ffffff h fe0000 h 010000 h 003900 h 004000 h 000100 h 0000c0 h 000000 h mb90v495g 001900 h 000900 h mb90f897/s/y/ys ff0000 h (with rom mirroring function enabled) peripheral ram area register extension io area rom area (ff bank image) rom area address #1 address #1 model : internal access memory : access disallowed * : on mb90f897/s/y/ys, to read ?fe0000 h ? to ?feffff h ? is to read out ?ff0000 h ? to ?ffffff h ?. rom area* mb90895 series ds07-13731-5e 15 i/o map (continued) address register abbreviation register read/ write resource initial value 000000 h (reserved area) * 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h to 000010 h (reserved area) * 000011 h ddr1 port 1 direction data register r/w port 1 00000000 b 000012 h ddr2 port 2 direction data register r/w port 2 00000000 b 000013 h ddr3 port 3 direction data register r/w port 3 000x0000 b 000014 h ddr4 port 4 direction data register r/w port 4 xxx00000 b 000015 h ddr5 port 5 direction data register r/w port 5 00000000 b 000016 h to 00001a h (reserved area) * 00001b h ader analog input permission register r/w 8/10-bit a/d converter 11111111 b 00001c h to 00001f h (reserved area) * 000020 h smr0 serial mode register 0 r/w uart0 00000000 b 000021 h scr0 serial control register 0 r/w, w 00000100 b 000022 h sidr0/ sodr0 serial input data register 0/ serial output data register 0 r, w xxxxxxxx b 000023 h ssr0 serial status register 0 r, r/w 00001x00 b 000024 h cdcr0 communication prescaler control register 0 r/w 0xxx1111 b 000025 h ses0 serial edge selection register 0 r/w xxxxxxx0 b 000026 h smr1 serial mode register 1 r/w uart1 00000000 b 000027 h scr1 serial control register 1 r/w, w 00000100 b 000028 h sidr1/ sodr1 serial input data register 1/ serial output data register 1 r, w xxxxxxxx b 000029 h ssr1 serial status data register 1 r, r/w 00001000 b 00002a h (reserved area) * 00002b h cdcr1 communication prescaler control register 1 r/w uart1 0xxx0000 b mb90895 series 16 ds07-13731-5e (continued) address register abbreviation register read/ write resource initial value 00002c h to 00002f h (reserved area) * 000030 h enir dtp/external interrupt permission register r/w dtp/external interrupt 00000000 b 000031 h eirr dtp/external interrupt source register r/w xxxxxxxx b 000032 h elvr detection level setting register r/w 00000000 b 000033 h r/w 00000000 b 000034 h adcs a/d control status register r/w 8/10-bit a/d converter 00000000 b 000035 h r/w, w 00000000 b 000036 h adcr a/d data register w, r xxxxxxxx b 000037 h r 00101xxx b 000038 h to 00003e h (reserved area) * 00003f h psccr pll/subclock control register r/w, w clock xxxx0000 b 000040 h ppgc0 ppg0 operation mode control register r/w, w 8/16-bit ppg timer 0/1 0x000xx1 b 000041 h ppgc1 ppg1 operation mode control register r/w, w 0x000001 b 000042 h ppg01 ppg0/1 count clock selection register r/w 000000xx b 000043 h (reserved area) * 000044 h ppgc2 ppg2 operation mode control register r/w, w 8/16-bit ppg timer 2/3 0x000xx1 b 000045 h ppgc3 ppg3 operation mode control register r/w, w 0x000001 b 000046 h ppg23 ppg2/3 count clock selection register r/w 000000xx b 000047 h to 00004f h (reserved area) * mb90895 series ds07-13731-5e 17 (continued) address register abbreviation register read/ write resource initial value 000050 h ipcp0 input capture data register 0 r 16-bit input/output timer xxxxxxxx b 000051 h xxxxxxxx b 000052 h ipcp1 input capture data register 1 r xxxxxxxx b 000053 h xxxxxxxx b 000054 h ics01 input capture control status register r/w 00000000 b 000055 h ics23 00000000 b 000056 h tcdt timer counter data register r/w 00000000 b 000057 h 00000000 b 000058 h tccs timer counter control status register r/w 00000000 b 000059 h (reserved area) * 00005a h ipcp2 input capture data register 2 r 16-bit input/output timer xxxxxxxx b 00005b h xxxxxxxx b 00005c h ipcp3 input capture data register 3 r xxxxxxxx b 00005d h xxxxxxxx b 00005e h to 000065 h (reserved area) * 000066 h tmcsr0 timer control status register r/w 16-bit reload timer 0 00000000 b 000067 h r/w xxxx0000 b 000068 h tmcsr1 r/w 16-bit reload timer 1 00000000 b 000069 h r/w xxxx0000 b 00006a h to 00006e h (reserved area) * 00006f h romm rom mirroring function selection register w rom mirroring function selection module xxxxxxx1 b 000070 h to 00007f h (reserved area) * 000080 h bvalr message buffer enabling regi ster r/w can controller 00000000 b 000081 h (reserved area) * 000082 h treqr send request register r/w can controller 00000000 b 000083 h (reserved area) * 000084 h tcanr send cancel register w can controller 00000000 b 000085 h (reserved area) * 000086 h tcr send completion register r/w can controller 00000000 b mb90895 series 18 ds07-13731-5e (continued) address register abbreviation register read/ write resource initial value 000087 h (reserved area) * 000088 h rcr receive completion register r/w can controller 00000000 b 000089 h (reserved area) * 00008a h rrtrr receive rtr register r/w can controller 00000000 b 00008b h (reserved area) * 00008c h rovrr receive overrun register r/w can controller 00000000 b 00008d h (reserved area) * 00008e h rier receive completion interrupt permission register r/w can controller 00000000 b 00008f h to 00009d h (reserved area) * 00009e h pacsr address detection control register r/w address matching detection function 00000000 b 00009f h dirr delay interrupt request generation/ release register r/w delay interrupt generation module xxxxxxx0 b 0000a0 h lpmcr lower power consumption mode control register w,r/w lower power consumption mode 00011000 b 0000a1 h ckscr clock selection register r,r/w clock 11111100 b 0000a2 h pilr port input level selection register r/w i/o 0000000x b 0000a3 h to 0000a7 h (reserved area) * 0000a8 h wdtc watchdog timer control regi ster r,w watchdog timer xxxxx111 b 0000a9 h tbtc time-base timer control register r/w,w time-base timer 1xx00100 b 0000aa h wtc watch timer control register r,r/w watch timer 1x001000 b 0000ab h to 0000ad h (reserved area) * 0000ae h fmcs flash memory control status register r,w,r/w 512k-bit flash memory 000x0000 b 0000af h (reserved area) * mb90895 series ds07-13731-5e 19 (continued) address register abbreviation register read/ write resource initial value 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 00000111 b 0000b2 h icr02 interrupt control register 02 00000111 b 0000b3 h icr03 interrupt control register 03 00000111 b 0000b4 h icr04 interrupt control register 04 00000111 b 0000b5 h icr05 interrupt control register 05 00000111 b 0000b6 h icr06 interrupt control register 06 00000111 b 0000b7 h icr07 interrupt control register 07 00000111 b 0000b8 h icr08 interrupt control register 08 00000111 b 0000b9 h icr09 interrupt control register 09 00000111 b 0000ba h icr10 interrupt control register 10 00000111 b 0000bb h icr11 interrupt control register 11 00000111 b 0000bc h icr12 interrupt control register 12 00000111 b 0000bd h icr13 interrupt control register 13 00000111 b 0000be h icr14 interrupt control register 14 00000111 b 0000bf h icr15 interrupt control register 15 00000111 b 0000c0 h to 0000ff h (reserved area) * 001ff0 h padr0 detection address setting register 0 (low-order) r/w address matching detection function xxxxxxxx b 001ff1 h detection address setting register 0 (middle-order) xxxxxxxx b 001ff2 h detection address setting register 0 (high-order) xxxxxxxx b 001ff3 h padr1 detection address setting register 1 (low-order) r/w xxxxxxxx b 001ff4 h detection address setting register 1 (middle-order) xxxxxxxx b 001ff5 h detection address setting register 1 (high-order) xxxxxxxx b 003900 h tmr0/ tmrlr0 16-bit timer register 0/16-bit reload register 0 r,w 16-bit reload timer 0 xxxxxxxx b 003901 h xxxxxxxx b 003902 h tmr1/ tmrlr1 16-bit timer register 1/16-bit reload register 1 r,w 16-bit reload timer 1 xxxxxxxx b 003903 h xxxxxxxx b 003904 h to 003909 h (reserved area) * mb90895 series 20 ds07-13731-5e (continued) address register abbreviation register read/ write resource initial value 00390a h fwr0 flash programing control register 0 r/w dual operation flash 00000000 b 00390b h fwr1 flash programing control register 1 r/w 00000000 b 00390c h ssr0 sector conversion set register r/w 00xxxxx0 b 00390d h to 00390f h (reserved area) * 003910 h prll0 ppg0 reload register l r/w 8/16-bit ppg timer xxxxxxxx b 003911 h prlh0 ppg0 reload register h r/w xxxxxxxx b 003912 h prll1 ppg1 reload register l r/w xxxxxxxx b 003913 h prlh1 ppg1 reload register h r/w xxxxxxxx b 003914 h prll2 ppg2 reload register l r/w xxxxxxxx b 003915 h prlh2 ppg2 reload register h r/w xxxxxxxx b 003916 h prll3 ppg3 reload register l r/w xxxxxxxx b 003917 h prlh3 ppg3 reload register h r/w xxxxxxxx b 003918 h to 00392f h (reserved area) * 003930 h to 003bff h (reserved area) * 003c00 h to 003c0f h ram (general-purpose ram) 003c10 h to 003c13 h idr0 id register 0 r/w can controller xxxxxxxx b to xxxxxxxx b 003c14 h to 003c17 h idr1 id register 1 r/w xxxxxxxx b to xxxxxxxx b 003c18 h to 003c1b h idr2 id register 2 r/w xxxxxxxx b to xxxxxxxx b 003c1c h to 003c1f h idr3 id register 3 r/w xxxxxxxx b to xxxxxxxx b 003c20 h to 003c23 h idr4 id register 4 r/w xxxxxxxx b to xxxxxxxx b 003c24 h to 003c27 h idr5 id register 5 r/w xxxxxxxx b to xxxxxxxx b 003c28 h to 003c2b h idr6 id register 6 r/w xxxxxxxx b to xxxxxxxx b mb90895 series ds07-13731-5e 21 (continued) address register abbreviation register read/ write resource initial value 003c2c h to 003c2f h idr7 id register 7 r/w can controller xxxxxxxx b to xxxxxxxx b 003c30 h 003c31 h dlcr0 dlc register 0 r/w xxxxxxxx b xxxxxxxx b 003c32 h 003c33 h dlcr1 dlc register 1 r/w xxxxxxxx b xxxxxxxx b 003c34 h 003c35 h dlcr2 dlc register 2 r/w xxxxxxxx b xxxxxxxx b 003c36 h 003c37 h dlcr3 dlc register 3 r/w xxxxxxxx b xxxxxxxx b 003c38 h 003c39 h dlcr4 dlc register 4 r/w xxxxxxxx b xxxxxxxx b 003c3a h 003c3b h dlcr5 dlc register 5 r/w xxxxxxxx b xxxxxxxx b 003c3c h 003c3d h dlcr6 dlc register 6 r/w xxxxxxxx b xxxxxxxx b 003c3e h 003c3f h dlcr7 dlc register 7 r/w xxxxxxxx b xxxxxxxx b 003c40 h to 003c47 h dtr0 data register 0 r/w xxxxxxxx b to xxxxxxxx b 003c48 h to 003c4f h dtr1 data register 1 r/w xxxxxxxx b to xxxxxxxx b 003c50 h to 003c57 h dtr2 data register 2 r/w xxxxxxxx b to xxxxxxxx b 003c58 h to 003c5f h dtr3 data register 3 r/w xxxxxxxx b to xxxxxxxx b 003c60 h to 003c67 h dtr4 data register 4 r/w xxxxxxxx b to xxxxxxxx b 003c68 h to 003c6f h dtr5 data register 5 r/w xxxxxxxx b to xxxxxxxx b 003c70 h to 003c77 h dtr6 data register 6 r/w xxxxxxxx b to xxxxxxxx b 003c78 h to 003c7f h dtr7 data register 7 r/w xxxxxxxx b to xxxxxxxx b mb90895 series 22 ds07-13731-5e (continued) initial values : 0 : initial value of this bit is ?0.? 1 : initial value of this bit is ?1.? x : initial value of this bit is undefined. * : ?reserved area? should not be written anything. result of reading from ?reserved area? is undefined. address register abbreviation register read/ write resource initial value 003c80 h to 003cff h (reserved area) * 003d00 h 003d01 h csr control status register r/w, r can controller 0xxxx001 b 00xxx000 b 003d02 h leir last event display register r/w 000xx000 b 003d03 h (reserved area) * 003d04 h 003d05 h rtec send/receive error counter r can controller 00000000 b 00000000 b 003d06 h 003d07 h btr bit timing register r/w 11111111 b x1111111 b 003d08 h ider ide register r/w xxxxxxxx b 003d09 h (reserved area) * 003d0a h trtrr send rtr register r/w 00000000 b 003d0b h (reserved area) * 003d0c h rfwtr remote frame receive wait register r/w can controller xxxxxxxx b 003d0d h (reserved area) * 003d0e h tier send completion interrupt permission register r/w can controller 00000000 b 003d0f h (reserved area) * 003d10 h 003d11 h amsr acceptance mask selection register r/w can controller xxxxxxxx b xxxxxxxx b 003d12 h 003d13 h (reserved area) * 003d14 h to 003d17 h amr0 acceptance mask register 0 r/w can controller xxxxxxxx b to xxxxxxxx b 003d18 h to 003d1b h amr1 acceptance mask register 1 r/w xxxxxxxx b to xxxxxxxx b 003d1c h to 003dff h (reserved area) * 003e00 h to 003eff h (reserved area) * 003ff0 h to 003fff h (reserved area) * mb90895 series ds07-13731-5e 23 interrupt sources, interrupt vectors , and interrupt control registers (continued) interrupt source ei 2 os readiness interrupt vector interrupt control register priority* 3 number address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? can controller reception completed (rx) #11 0b h ffffd0 h icr00 0000b0 h * 1 can controller transmission completed (tx) / node status transition (ns) #12 0c h ffffcc h reserved #13 0d h ffffc8 h icr01 0000b1 h reserved #14 0e h ffffc4 h can wakeup #15 0f h ffffc0 h icr02 0000b2 h * 1 time-base timer #16 10 h ffffbc h 16-bit reload timer 0 #17 11 h ffffb8 h icr03 0000b3 h * 1 8/10-bit a/d converter #18 12 h ffffb4 h 16-bit free-run timer overflow #19 13 h ffffb0 h icr04 0000b4 h * 1 reserved #20 14 h ffffac h reserved #21 15 h ffffa8 h icr05 0000b5 h * 1 ppg timer ch.0, ch.1 underflow #22 16 h ffffa4 h input capture 0-input #23 17 h ffffa0 h icr06 0000b6 h * 1 external interrupt (int4/int5) #24 18 h ffff9c h input capture 1-input #25 19 h ffff98 h icr07 0000b7 h * 2 ppg timer ch.2, ch.3 underflow #26 1a h ffff94 h external interrupt (int6/int7) #27 1b h ffff90 h icr08 0000b8 h * 1 watch timer #28 1c h ffff8c h reserved #29 1d h ffff88 h icr09 0000b9 h * 1 input capture 2-input input capture 3-input #30 1e h ffff84 h reserved #31 1f h ffff80 h icr10 0000ba h * 1 reserved #32 20 h ffff7c h reserved #33 21 h ffff78 h icr11 0000bb h * 1 reserved #34 22 h ffff74 h reserved #35 23 h ffff70 h icr12 0000bc h * 1 16-bit reload timer 1 #36 24 h ffff6c h low mb90895 series 24 ds07-13731-5e (continued) : available : unavailable : available, el 2 os stop function is provided. : available when a cause of interr upt sharing a same icr is not used. *1 : ? peripheral functions sharing an icr register have the same interrupt level. ? if peripheral functions share an icr register, only one function is available when using extended intelligent i/o service. ? if peripheral functions share an icr register, a functi on using extended intelligent i/o service does not allow interrupt by another function. *2 : only input capture 1 is ready for ei 2 os. because ppg is not ready for ei 2 os, disable ppg interrupt when using ei 2 os with input capture 1. *3 : priority when two or more interrupts of a same level occur simultaneously. interrupt source ei 2 os readiness interrupt vector interrupt control register priority* 3 number address icr address uart1 reception completed #37 25 h ffff68 h icr13 0000bd h * 1 high uart1 transmission completed #38 26 h ffff64 h uart0 reception completed #39 27 h ffff60 h icr14 0000be h * 1 uart0 transmission completed #40 28 h ffff5c h flash memory #41 29 h ffff58 h icr15 0000bf h * 1 delay interrupt generation module #42 2a h ffff54 h low mb90895 series ds07-13731-5e 25 flash memory configuration ? sector configuration of 512 kbit flash memory ff0000 h ff0fff h ff1000 h ff1fff h ff2000 h ff2fff h ff3000 h ff3fff h 70000 h 70fff h 71000 h 71fff h 72000 h 72fff h 73000 h 73fff h ff4000 h ff7fff h ff8000 h ffbfff h ffc000 h ffcfff h ffd000 h ffdfff h 74000 h 77fff h 78000 h 7bfff h 7c000 h 7cfff h 7d000 h 7dfff h ffe000 h ffefff h fff000 h ffffff h 7e000 h 7efff h 7f000 h 7ffff h lower bank upper bank flash memory cpu address writer address* sa0 (4 kbytes) sa1 (4 kbytes) sa2 (4 kbytes) sa3 (4 kbytes) * : ?writer address? is an address e quivalent to cpu address, which is used when data is written on flash memory , using parallel writer. when writing/ deleting data with general-purpose writer, the writer address is used for writing and deleting. sa4 (16 kbytes) sa5 (16 kbytes) sa6 (4 kbytes) sa7 (4 kbytes) sa8 (4 kbytes) sa9 (4 kbytes) mb90895 series 26 ds07-13731-5e electric characteristics 1. absolute maximum rating *1: the parameter is based on v ss = av ss = 0.0 v. *2 : avcc and avr should not exceed vcc. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avr v ss ? 0.3 v ss + 6.0 v av cc avr* 2 input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma *7 total maximum clamp current | i clamp | ? 20 ma *7 ?l? level maximum output current i ol1 ? 15 ma normal output* 4 i ol2 ? 40 ma high-current output* 4 ?l? level average output current i olav1 ? 4 ma normal output* 5 i olav2 ? 30 ma high-current output* 5 ?l? level maximum total output current i ol1 ? 125 ma normal output i ol2 ? 160 ma high-current output ?l? level average total output current i olav1 ? 40 ma normal output* 6 i olav2 ? 40 ma high-current output* 6 ?h? level maximum output current i oh1 ?? 15 ma normal output* 4 i oh2 ?? 40 ma high-current output* 4 ?h? level average output current i ohav1 ?? 4 ma normal output* 5 i ohav2 ?? 30 ma high-current output* 5 ?h? level maximum total output current i oh1 ?? 125 ma normal output i oh2 ?? 160 ma high-current output ?h? level average total output current i ohav1 ?? 40 ma normal output* 6 i ohav2 ?? 40 ma high-current output* 6 power consumption p d ? 297 mw operating temperature t a ?40 + 105 c other than mb90f897y/ys ?40 + 125 c *8 other than mb90f897y/ys ?40 + 150 c *8, *9 mb90f897y/ys storage temperature tstg ?55 + 150 c mb90895 series ds07-13731-5e 27 (continued) *3 : v i and v o should not exceed vcc + 0.3 v. however, if the ma ximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : a peak value of an applicable one pi n is specified as a maximum output current. *5 : an average current value of an applicable one pin with in 100 ms is specified as an average output current. (average value is found by multiplyi ng operating current by operating rate.) *6 : an average current value of all pins within 100 ms is specified as an average total output current. (average value is found by multiplying o perating current by operating rate.) *7 : ? applicable to pins: p10 to p17, p20 to p27, p30 to p33, p35, p36, p37, p40 to p44, p50 to p57 note: p35 and p36 are mb90f897s/ys only. ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistanc e should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the powe r supply is provided from the pins and the resulting supply voltage may not be suff icient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits: *8 : users considering application exceeding t a = +105 c are advised to contact their fujitsu microelec- tronics representatives beforeha nd for reliability limitations. *9 : use the pb circuit board which has 4 or more layers. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits +b input (0 v to 16 v) limiting resistance protective diode mb90895 series 28 ds07-13731-5e 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : use a ceramic capacitor, or a capacitor of similar frequency characteristics. on the vcc pin, use a bypass capacitor that has a larger capacity than that of cs. refer to the following figure for con nection of smoothing capacitor cs. *2: users considering application exceeding t a = +105 c are advised to contact their fujitsu microelectron- ics representatives beforehand for reliability limitations. *3 : use the pb circuit board which has 4 or more layers. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 3.5 5.0 5.5 v under normal operation 3.0 ? 5.5 v retain status of stop operation 4.0 ? 5.5 v accuracy guarantee voltage of a/d converter smoothing capacitor c s 0.1 ? 1.0 f*1 operating temperature t a ?40 ?+ 105 c other than mb90f897y/ys ?40 ?+ 125 c *2 other than mb90f897y/ys ?40 ?+ 150 c *2, *3 mb90f897y/ys c c s ? c pin connection diagram mb90895 series ds07-13731-5e 29 3. dc characteristics ? mb90f897/s (models that support + 125 c) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 125 c) * : test conditions of power supply current ar e based on a device using external clock. (continued) parame- ter sym bol pin name conditions value unit remarks min typ max ?h? level input voltage v ihs cmos hysteresis input pin ?0.8 v cc ?v cc + 0.3 v when selected cmos hyster- esis v iha automotive input pin ?0.8 v cc ?v cc + 0.3 v when selected automotive v ihc cmos input pin (p32, p40) ?0.7 v cc ?v cc + 0.3 v when selected cmos v ihm md input pin ? v cc ? 0.3 ? v cc + 0.3 v ?l? level input voltage v ils cmos hysteresis input pin ?v ss ? 0.3 ? 0.2 v cc v when selected cmos hyster- esis v ila automotive input pin ?v ss ? 0.3 ? 0.5 v cc v when selected automotive v ilc cmos input pin (p32, p40) ?v ss ? 0.3 ? 0.3 v cc v when selected cmos v ilm md input pin ? v ss ? 0.3 ? v ss + 0.3 v ?h? level output voltage v oh1 pins other than p14 to p17 v cc = 4.5 v, i oh = ?4.0 ma v cc ? 0.5 ? ? v v oh2 p14 to p17 v cc = 4.5 v, i oh = ?14.0 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 pins other than p14 to p17 v cc = 4.5 v, i ol = 4.0 ma ??0.4v v ol2 p14 to p17 v cc = 4.5 v, i ol = 20.0 ma ??0.4v input leak current i il all input pins v cc = 5.5 v, v ss < v i < v cc ?5 ? + 5 a power supply current* i cc v cc v cc = 5.0 v, internally operating at 16 mhz, normal operation. ?2530ma v cc = 5.0 v, internally operating at 16 mhz, writing on flash memory. ? 45 50 ma mb90f897/s v cc = 5.0 v, internally operating at 16 mhz, deleting on flash memory. ? 45 50 ma mb90f897/s mb90895 series 30 ds07-13731-5e (continued) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 125 c) * : test conditions of power supply current ar e based on a device using external clock. parameter sym- bol pin name conditions value unit remarks min typ max power supply current* i ccs v cc v cc = 5.0 v, internally operating at 16 mhz, sleeping. ?812ma i cts v cc = 5.0 v, internally operating at 2 mhz, transition from main clock mode, in time-base timer mode. ?0.20.35ma i ctspii v cc = 5.0 v, internally operating at 16 mhz, transition from pll clock mode, in time-base timer mode. ?3 5ma i ccl v cc = 5.0 v, internally operating at 8 khz, subclock operation, t a = + 25 c ? 40 100 a i ccls v cc = 5.0 v, internally operating at 8 khz, subclock, sleep mode, t a = + 25 c ?1050 a i cct v cc = 5.0 v, internally operating at 8 khz, watch mode, t a = + 25 c ?830 a i cch stopping, t a = + 25 c ?525 a input capacity c in other than av cc , av ss , avr, c, v cc , v ss ? ?515pf pull-up resistor r up rst ? 25 50 100 k pull-down resistor r down md2 ? 25 50 100 k flash product is not provided with pull-down resistor. mb90895 series ds07-13731-5e 31 ? ? mb90f897y/ys (models that support + 150 c) (under development) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 150 c) * : test conditions of power supply current ar e based on a device using external clock. (continued) parameter sym bol pin name conditions value unit remarks min typ max ?h? level input voltage v ihs cmos hysteresis input pin ? 0.8 v cc ?v cc + 0.3 v when selected cmos hyster- esis v iha automotive input pin ? 0.8 v cc ?v cc + 0.3 v when selected automotive v ihc cmos input pin (p32, p40) ? 0.7 v cc ?v cc + 0.3 v when selected cmos v ihm md input pin ? v cc ? 0.3 ? v cc + 0.3 v ?l? level input voltage v ils cmos hysteresis input pin ?v ss ? 0.3 ? 0.2 v cc v when selected cmos hyster- esis v ila automotive input pin ?v ss ? 0.3 ? 0.5 v cc v when selected automotive v ilc cmos input pin (p32, p40) ?v ss ? 0.3 ? 0.3 v cc v when selected cmos v ilm md input pin ? v ss ? 0.3 ? v ss + 0.3 v ?h? level output volt- age v oh1 pins other than p14 to p17 v cc = 4.5 v, i oh = ?3.0 ma v cc ? 0.5 ? ? v v oh2 p14 to p17 v cc = 4.5 v, i oh = ?12.0 ma v cc ? 0.5 ? ? v ?l? level output volt- age v ol1 pins other than p14 to p17 v cc = 4.5 v, i ol = 3.0 ma ??0.4v v ol2 p14 to p17 v cc = 4.5 v, i ol = 16 ma ??0.4v input leak current i il all input pins v cc = 5.5 v, v ss < v i < v cc ?5 ? +5 a power supply current* i cc v cc v cc = 5.0 v, internally operating at 16 mhz, normal operation. ?2532ma v cc = 5.0 v, internally operating at 16 mhz, writing on flash memory. t a = ?40 c to +125 c ?4550maup to + 125 c v cc = 5.0 v, internally operating at 16 mhz, deleting on flash memory. t a = ?40 c to +125 c ?4550maup to + 125 c mb90895 series 32 ds07-13731-5e (continued) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 150 c) * : test conditions of power supply current ar e based on a device using external clock. parameter sym- bol pin name conditions value unit remarks min typ max power supply current* i ccs v cc v cc = 5.0 v, internally operating at 16 mhz, sleeping. ?814ma i cts v cc = 5.0 v, internally operating at 2 mhz, transition from main clock mode, in time-base timer mode. t a = ? 40 c to +125 c ? 0.2 0.35 ma up to + 125 c v cc = 5.0 v, internally operating at 2 mhz, transition from main clock mode, in time-base timer mode. t a = + 125 c to +150 c ?0.2t.b.dma i ctspii v cc = 5.0 v, internally operating at 16 mhz, transition from pll clock mode, in time-base timer mode. ?3 7ma i ccl v cc = 5.0 v, internally operating at 8 khz, subclock operation, t a = + 25 c ? 40 100 a i ccls v cc = 5.0 v, internally operating at 8 khz, subclock, sleep mode, t a = + 25 c ?1050 a i cct v cc = 5.0 v, internally operating at 8 khz, watch mode, t a = + 25 c ?830 a i cch stopping, t a = + 25 c ?525 a input capacity c in other than av cc , av ss , avr, c, v cc , v ss ? ?515pf pull-up resistor r up rst ? 25 50 100 k pull-down resistor r down md2 ? 25 50 100 k flash product is not provided with pull-down resistor. mb90895 series ds07-13731-5e 33 4. ac characteristics (1) clock timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3?8mhz when crystal or ceramic resonator is used 3 ? 16 mhz external clock 4 ? 16 mhz pll multiplied by 1 4 ? 8 mhz pll multiplied by 2 4 ? 5.33 mhz pll multiplied by 3 4 ? 4 mhz pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz mb90f897/y only clock cycle time t hcyl x0, x1 125 ? 333 ns t lcyl x0a, x1a ? 30.5 ? s mb90f897/y only input clock pulse width p wh , p wl x0 10 ? ? ns set duty factor at 30% to 70% as a guideline. p wlh ,p wll x0a ? 15.2 ? s mb90f897/y only input clock rise time and fall time t cr , t cf x0 ? ? 5 ns when external clock is used internal operation clock frequency f cp ? 1.5 ? 16 mhz when main clock is used f lcp ? ? 8.192 ? khz when sub clock is used, mb90f897/y only internal operation clock cycle time t cp ? 62.5 ? 666 ns when main clock is used t lcp ? ? 122.1 ? s when sub clock is used, mb90f897/y only x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll ? clock timing mb90895 series 34 ds07-13731-5e 16 12 8 9 4 34 8 16 1.5 5.5 4.0 3.0 3.5 3 4 8 16 12 1.5 power voltage v cc (v) internal clock f cp (mhz) operation guarantee range of mb90f897/s/y/ys pll operation guarantee range internal clock f cp (mhz) external clock f c (mhz)* 4 x 3 x 2 x 1 x 1/2 x (no multiplication) relation between internal operation clock frequency and power supply voltage relation among external clock frequency and internal clock frequency ? pll operation guarantee range a/d converter accuracy guarantee range * : fc is 8 mhz at maximum when crystal or ceramic resonator circuit is used. mb90895 series ds07-13731-5e 35 rating values of alternating current is defined by the measurement reference voltage values shown below: (2) reset input timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) *1 : oscillation time of oscillator is time that the amplit ude reached the 90%. in the crys tal oscillator, the oscillation time is between several ms to tens of ms. in ce ramic oscillator, the oscillation time is between hundreds of s to several ms. in the external clock, the oscillation time is 0 ms. *2 : except for mb90f897s/ys. *3 : refer to ?(1) clock timing? ratings for t cp (internal operation clock cycle time). parameter symbol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 16 t cp * 3 ? ns normal operation oscillation time of oscillator* 1 + 100 s + 16 t cp * 3 ?? in sub clock* 2 , sub sleep* 2 , watch* 2 and stop mode 100 ? s in timebase timer v ih v il 2.4 v 0.8 v hysteresis input pin ? output signal waveform output pin ? input signal waveform t rstl 0.2 v cc 0.2 v cc 100 s + 16 t cp rst x0 ? in sub clock, sub sleep, watch and stop mode internal operation clock internal reset oscillation time of oscillator wait time for stabilizing oscillation execute instruction 90% of amplitude mb90895 series 36 ds07-13731-5e (3) power-on reset (v ss = av ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, raise the power smoothl y by suppressing variation of voltages as shown below. when raising the power, do not use pll clock. however, if voltage drop is 1v/s or less, use of pll clock is allowed during operation. parameter symbol pin name conditions value unit remarks min max power supply rise time t r v cc ? 0.05 30 ms power supply shutdown time t off v cc 1 ? ms repeated operation v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3.0 v limiting the slope of rising within 50 mv/ms is recommended. ram data hold period mb90895 series ds07-13731-5e 37 (4) uart0/uart1 timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). notes: ? ac rating in clk synchronous mode. ? c l is a load capacitance value on pins for testing. parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0/sck1 internal shift clock mode output pin is : c l = 80 pf+1ttl 8 t cp * ? ns sck sot delay time t slov sck0/sck1, sot0/sot1 ?80 + 80 ns valid sin sck t ivsh sck0/sck1, sin0/sin1 100 ? ns sck valid sin hold time t shix sck0/sck1, sin0/sin1 60 ? ns serial clock ?h? pulse width t shsl sck0/sck1 external shift clock mode output pin is : c l = 80 pf+1ttl 4 t cp * ? ns serial clock ?l? pulse width t slsh sck0/sck1 4 t cp * ? ns sck sot delay time t slov sck0/sck1, sot0/sot1 ? 150 ns valid sin sck t ivsh sck0/sck1, sin0/sin1 60 ? ns sck valid sin hold time t shix sck0/sck1, sin0/sin1 60 ? ns mb90895 series 38 ds07-13731-5e ? internal shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v v ih v il v ih v il ? external shift clock mode sck sot sin t slsh t shsl t slov t ivsh t shix v il v il v ih v ih 2.4 v 0.8 v v ih v il v ih v il mb90895 series ds07-13731-5e 39 (5) timer input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). (6) trigger input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh tin0, tin1 ? 4 t cp * ? ns t tiwl in0 to in3 parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl int4 to int7, adtg ? 3 t cp * ? ns v ih v ih v il v il t tiwh t tiwl tin0, tin1, in0 to in3 ? timer input timing v ih v ih v il v il t trgh t trgl int4 to int7, adtg ? trigger input timing mb90895 series 40 ds07-13731-5e 5. a/d converter (v cc = av cc = 5.0 v 10 % , 3.0 v avr ? av ss , v ss = av ss = 0.0 v, t a = ? 40 c to +125 c/ +150 c (only mb90f897y/ys)) *1 : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). *2 : if a/d converter is not operating, a current wh en cpu is stopped is applicable (vcc=avcc=avr=5.0 v). parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 1 lsb = (avr ? av ss ) /1024 full-scale transition voltage v fst an0 to an7 avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v compare time ?? 66 t cp * 1 ?? ns with 16 mhz machine clock 5.5 v av cc 4.5 v 88 t cp * 1 ?? ns with 16 mhz machine clock 4.5 v > av cc 4.0 v sampling time ?? 32 t cp * 1 ?? ns with 16 mhz machine clock 5.5 v av cc 4.5 v 128 t cp * 1 ?? ns with 16 mhz machine clock 4.5 v > av cc 4.0 v analog port input current i ain an0 to an7 ?? 10 a analog input voltage v ain an0 to an7 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 a*2 reference voltage supplying current i r avr ? 165 250 a i rh avr ?? 5 a*2 variation among channels ? an0 to an7 ?? 4lsb mb90895 series ds07-13731-5e 41 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. linear error : deviation between a line ac ross zero-transition line (?00 0000 0000? ?00 0000 0001?) and full-scale transition line (?11 1111 1110? ?11 1111 1111?) and actual conversion characteristics. differential linear error : deviation of input voltage, which is requir ed for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} v nt total error total error of digital output ?n? = v nt ? { 1 lsb (n ? 1) + 0.5 lsb} [lsb] 1 lsb 1 lsb = (ideal value) avr ? av ss [v] 1024 v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] v nt : a voltage at which digital output transits from (n-1) to n. digital output actual conversion characteristics (actually-measured value) actual conversion characteristics analog input ideal characteristics mb90895 series 42 ds07-13731-5e (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr av ss avr n + 1 n n ? 1 n ? 2 v ot (actual measurement v alue) v fst (actual measurement v alue) actua l conversion char a cteristics {1 lsb (n ? 1) + v ot } actua l conversion char a cteristics ideal char a cteristics ideal char a cteristics actua l conversion char a cteristics v ( n + 1) t (actual measurement v alue) v nt (actual measurement v alue) actua l conversion char a cteristics v nt (actual measurement v alue) differential linear error linear error linear error of digital output n = v nt ? { 1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linear error of digital output n = v ( n + 1 ) t ? v nt 1 lsb ? 1lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .? digital output digital output analog input analog input mb90895 series ds07-13731-5e 43 7. notes on a/d converter section mb90895 series 44 ds07-13731-5e (continued) ? to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the resi stor value and operating frequency or decrease the external impedance so that the sampling ti me is longer than the minimum value. the relationship between the exter nal impedance and minimum sampling time ? if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. mb90895 series ds07-13731-5e 45 8. flash memory program/erase characteristics* 1 *1 : for mb90f897y/ys, it is prohibited to write or erase data in the range of t a = + 125 c to + 150 c. *2 : this value comes from the techno logy qualification (using arrhenius equ ation to translate high temperature measurements into normalized value at + 85 c) . parameter conditions value unit remarks min typ max sector erase time (4 kb sector) t a = + 25 c, v cc = 5.0 v ? 0.2 0.5 s excludes 00 h programming prior to erasure sector erase time (16 kb sector) ? 0.5 7.5 s excludes 00 h programming prior to erasure chip erase time ? 2.6 ? s excludes 00 h programming prior to erasure word (16 bit width) programming time ? 16 3,600 s except for the over head time of the system program/erase cycle ? 10,000 ?? cycle flash data retention time average t a = + 85 c 20 ?? years *2 mb90895 series 46 ds07-13731-5e example characteristics ? mb90f897 (continued) i cc ? v cc t a = +25 c, in external clock operation f = internal operating frequency i ccs ? v cc t a = +25 c, in external clock operation f = internal operating frequency i ccl ? v cc t a = +25 c, in external clock operation f = internal operating frequency i cc (ma) v cc (v) 2.5 3.5 4.5 5.5 6.5 0 5 10 15 20 25 30 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccs (ma) v cc (v) 2.5 3.5 4.5 5.5 6.5 0 2 4 6 8 10 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccl (a) v cc (v) 3 4567 0 50 200 250 300 350 f = 8 khz 100 150 mb90895 series ds07-13731-5e 47 (continued) i ccls ? v cc t a = +25 c, in external clock operation f = internal operating frequency i cct ? v cc t a = +25 c, in external clock operation f = internal operating frequency i cch ? v cc stopping, t a = +25 c i ccls (a) v cc (v) 3 4567 0 3 9 11 13 15 f = 8 khz 5 7 1 4 6 8 10 12 14 2 i cct (a) v cc (v) 3 4567 0 6 9 10 f = 8 khz 2 4 1 3 5 7 8 i cch (a) v cc (v) 2 4567 0 30 5 10 15 20 25 3 mb90895 series 48 ds07-13731-5e (continued) (v cc - v oh ) ? i oh t a = +25 c, v cc = 4.5 v v ol ? i ol t a = +25 c, v cc = 4.5 v ?h? level input voltage/ ?l? level input voltage v in ? v cc t a = +25 c v cc - v oh (mv) i oh (ma) 0 468 10 0 600 900 1000 200 400 100 300 500 700 800 2 1 579 3 v ol (mv) i ol (ma) 0 4681 0 0 600 900 1000 200 400 100 300 500 700 800 2 v in (v) v cc (v) 2.5 3.5 4 4.5 6 0 3 5 1 2 4 3 5 5.5 v ih v il mb90895 series ds07-13731-5e 49 ordering information part number package remarks mb90f897pmt mb90f897spmt MB90F897YPMT mb90f897yspmt 48-pin plastic lqfp (fpt-48p-m26) mb90895 series 50 ds07-13731-5e package dimention please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 4 8 -pin plastic lqfp lea d pitch 0.50 mm p a ck a ge width p a ck a ge length 7 7 mm lea d s h a pe gu llwing s e a ling method plastic mold mou nting height 1.70 mm max weight 0.17 g code (reference) p-lfqfp48 -7 7-0.50 4 8 -pin plastic lqfp (fpt-4 8 p-m26) (fpt-48p-m26) c 2003 fujitsu limited f48040s-c-2-2 24 13 362 5 48 37 index sq 9.000.20(.354.008)sq 0.1450.055 (.006.002) 0.08(.003) "a" 0?~8? .059 ?.004 +.008 ?0.10 +0.20 1.50 0.600.15 (.024.006) 0.100.10 (.004.004) (stand off) 0.25(.010) details of "a" part 1 12 0.08(.003) m (.008.002) 0.200.05 0.50(.020) lead no. (mounting height) .276 ?.004 +.016 ?0.10 +0.40 7.00 * dimens ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2003 -2008 fujits u microelectronics limited f48 040s -c-2-3 note 1) * : these dimensions include resin protrusion. note 2) pin s width a nd pins thickness inclu de pla ting thickness. note 3 )pin s width do not inclu de tie bar cu tting rema inder. mb90895 series ds07-13731-5e 51 main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results ?? added the following part numbers under development. mb90f897y, mb90f897ys 1 features added as follows. ? models that support + 150 c (mb90f897y/ys) 8 pin description corrected the func tion of pin sck0 on pin number 43. uart1 uart0 11 handling devices correct ed the description for ? ? handling unused pins?. unused input pins unused i/o pins 12 ?? support for + 125 c? ?? support for + 125 c / + 150 c? 13 block diagram corrected the arrow for ?pin x0 and x1? in the clock control circuit. ?input ? ?input/output ? corrected the arrow for ?pin ti n0 and pin tin1? in 16-bit reload timer (2ch). ?output ? ? input ? 23 interrupt sources, interrupt vectors, and interrupt control registers corrected footnotes in the address column for icr05 and icr07 of the interrupt control register. 0000b5 h * 2 0000b5 h * 1 10000b7 h * 1 0000b7 h * 2 24 corrected the description for footnote *2. 16-bit reload timer input capture 1 ? peripheral resources deleted the section refer to the hardware manual, for details of peripheral re- sources. 25 flash memory configurat ion changed the item name from ?peripheral resourc- es? to ?flash memory configuration?. 26 electric characteristics 1. absolute maximum rating item: added the rating value for mb90f897y/ys to the operating temperature. min: ? 40 c, max: + 150 c 27 added footnote*9. 28 2. recommended operating conditions item: added the rating value for mb90f897y/ys to the operating temperature. min: ? 40 c,max: + 150 c added footnote *3. 31, 32 3. dc characteristics added dc characteristics for ?mb90f897y/ys?. 33 to 40 4. ac characteristics changed the conditi on description in the upper right of the table. t a = ? 40 c to +125 c t a = ? 40 c to +125 c/ + 150 c (only mb90f897y/ys) 5. a/d converter 49 ordering information added the following part numbers. MB90F897YPMT, mb90f897yspmt mb90895 series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porating the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department |
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